1. Field of the Invention
This invention relates generally to delay locked loops, and particularly to multiple phase generation using delay locked loops.
2. Description of Related Art
In modern high frequency integrated circuits, it is often necessary to generate internal clocks with predetermined phase relationships to a reference clock. Conventionally, a Phase Locked Loop (PLL) or Delay Locked Loop (DLL) has been used to generate these predetermined phase relationships. For example, many reference input clocks may not have a 50% duty cycle. However, with modern semiconductor devices, such as Double Data Rate (DDR) Dynamic Random Access Memory (DRAM) devices, two data cycles may occur within one clock cycle. An internal clock with a 50% duty cycle may be needed so the two data cycles may be accurately sampled at the rising edge and the falling edge of the clock. Alternatively, an additional clock with a phase delay of 180 degrees relative to the reference clock may be used to sample one data slice and the reference clock may be used to sample the other data slice. Furthermore, modern semiconductor devices, such as DRAM and processors, may require multiple clocks with defined phase relationships to trigger events at various times during a clock cycle. For example, it may be desirable to have clocks with phase relationships of 90°, 180°, 270°, and 360° relative to a reference clock.
Various solutions exist for generating these desired duty cycles and clocks with defined phase relationships; these solutions are conventionally referred to as Duty Cycle Correctors (DCC) and phase generators. Conventionally, phase generators may be constructed as a DLL using either analog or digital delay lines. Analog delay lines may allow more precise control but may consume more silicon space or “real estate,” consume more power, and take longer to achieve lock. Digital delay lines, on the other hand, are easier to design, smaller, and may consume less power. Digital delay lines may achieve lock faster than analog delay lines; however, digital delay lines may not be able to achieve the continuous fine-tuning available in an analog delay line.
A conventional phase generator constructed as a DLL is shown in FIG. 1. A clock input 5 (also referred to as a ph0 signal) connects to a first delay line 10. A ph180 signal 15, generated by the first delay line 10, connects to a second delay line 20. A ph360 signal 25, from the output of the second delay line 20, feeds back to a phase detector 30. The phase detector 30 compares the phase of the clock input 5 to the second delay line 20 output. Because of the comparison, the phase detector 30 generates the delay control signal 35 controlling the delay lines (10 and 20) to either increase or decrease the delay. The first delay line 10 and second delay line 20 are of similar construction such that the delay control signal 35, connected to both delay lines (10 and 20), causes both delay lines to generate the same amount of delay. With this closed loop, the DLL “locks” on to the clock input 5 so that the ph360 signal 25 is at substantially the same phase and frequency as the clock input 5.
Because the two delay lines generate equivalent delays, the ph180 signal 15 is at the same frequency as, and 180 degrees out of phase with, the clock input 5. The phase detector 30 only compares rising edge to rising edge or falling edge to falling edge. As a result, the phase generator will lock and generate the ph180 signal 15 at 180 degrees out of phase regardless of the duty cycle of the clock input 5.
However conventional digital DLL phase generators have their limits. Due to the structure of the delay lines, there is a minimum delay and a maximum delay possible through each delay line. The lowest frequency input clock that the DLL is able to lock to is defined by the maximum delay. For example, if the maximum delay through each delay line is 50 nSec, the total maximum delay is 100 nSec, and the DLL can lock to clock frequencies of 10 Mhz or higher. On the other hand, if the minimum delay through each delay line is 2.5 nSec, the total minimum delay is 5 nSec. Consequently, if the input clock is faster than 200 Mhz (i.e., a clock period of less than 5 nSec), the DLL cannot lock to the clock input because the ph360 signal 25 cannot be brought any closer to the ph0 signal 5 than the minimum delay. Conventionally, DLL design involves considerations such as locking range (i.e., maximum delay) versus die size and power consumption.
Other phase generator configurations have been proposed for increasing the clock frequencies beyond the minimum delay of the combined delay elements of a ALL. A phase generator 40 constructed as a DLL, which increases the operation frequency, is shown in FIG. 2. A phase generator 40 includes a phase detector 70, a first delay line 50, a second delay line 55, a first phase aligner 75 and a second phase aligner 85. A clock input 45 connects to the first delay line 50. A dly180 signal 60 is generated by the first delay line 50 and connects to the second delay line 55. A ph360 signal 95 is generated by the second delay line 55 and feeds back to the phase detector 70.
The clock input 45 also connects to the first phase aligner 75. A ph0 signal 80 is generated by the first phase aligner 75 and feeds back to the phase detector 70. A second phase aligner 85 connects to the dly180 signal 60 and generates a ph180 signal 90. The first and second delay lines 50, 55, respectively, are configured similarly with the same selectable delay increments. Consequently, both delay lines 50, 55 have substantially the same delay magnitude based on a phase adjustment signal 65, which is generated by the phase detector 70 and selects the delay increments, and as a result, the delay magnitude for both delay lines.
An alignment adjustment signal 71, generated by the phase detector 70, controls the alignment magnitudes (i.e., delay) of the first and second phase aligners 75, 85. The second phase aligner 85 is generally configured with delay increments that are one-half the size of the delay increments for the first phase aligner 75. Consequently, for any given value on the alignment adjustment signal 71, the second phase aligner 85 generates a delay magnitude that is substantially one-half the delay magnitude generated by the first phase aligner 75.
While such a configuration may allow for a higher frequency input clock 45, the forward path intrinsic delay is no longer substantially zero. As illustrated, the forward path intrinsic delay is the intrinsic delay for the ph0 signal 80 through the first phase aligner 75 and has been purposely increased to be out of phase with the ph0 signal 80.
There is a need for a digital phase generator that can lock and operate at higher frequencies without affecting the overall locking range of the DLL within the digital phase generator and without unduly inserting excessive delay in the forward path.